View K4G323222M-PL70_6610477.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

k4g323222m cmos sgram the k4g323222m is 33,554,432 bits synchronous high data rate dynamic ram organized as 2 x 524,288 words by 32 bits, fabricated with samsung s high performance cmos technol- ogy. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst length, and programmable latencies allows the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications. write per bit and 8 columns block write improves performance in graphics systems. ? 3.3v power supply ? lvttl compatible with multiplexed address ? dual bank operation ? mrs cycle with address key programs -. cas latency (2, 3) -. burst length (1, 2, 4, 8 & full page) -. burst type (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock ? burst read single-bit write operation ? dqm 0-3 for byte masking ? auto & self refresh ? 32ms refresh period (2k cycle) ? 100 pin pqfp, tqfp (14 x 20 mm) graphics features ? smrs cycle. -. load mask register -. load color register ? write per bit(old mask) ? block write(8 columns) general description features functional block diagram 512k x 32bit x 2 banks synchronous graphic ram t i m i n g r e g i s t e r clk cke cs ras cas we dsf dqmi block write control logic dqi p r o g r a m i n g r e g i s t e r l a t e n c y & b u r s t l e n g t h 512kx32 cell array 512kx32 cell array serial counter column address buffer row decorder bank selection address register refresh counter row address buffer i n p u t b u f f e r mask register color register mux write control logic m a s k c o l u m n d e c o r d e r s e n s e a m p l i f i e r column mask (i=0~31) dqmi clock address(a 0 ~a 10 ,ba) dqmi o u t p u t b u f f e r ordering information part no. max freq. interface package k4g323222m-pc/l45 222mhz lvttl 100 pqfp k4g323222m-pc/l50 200mhz k4g323222m-pc/l55 183mhz k4g323222m-pc/l60 166mhz k4g323222m-pc/l70 143mhz k4g323222m-pc/l80 125mhz k4g323222m-qc/l45 222mhz lvttl 100 tqfp k4g323222m-qc/l50 200mhz k4g323222m-qc/l55 183mhz k4g323222m-qc/l60 166mhz k4g323222m-qc/l70 143mhz k4g323222m-qc/l80 125mhz samsung electronics reserves the right to change products or specification without notice. *
k4g323222m cmos sgram dq29 v ssq dq30 dq31 v ss n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c v dd dq0 dq1 v ssq dq2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pin configuration (top view) d q 3 v d d q d q 4 d q 5 v s s q d q 6 d q 7 v d d q d q 1 6 d q 1 7 v s s q d q 1 8 d q 1 9 v d d q v d d v s s d q 2 0 d q 2 1 v s s q d q 2 2 d q 2 3 v d d q d q m 0 d q m 2 w e c a s r a s c s b a a 9 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 a 7 a 6 a 5 a 4 v ss a 10 n.c n.c n.c n.c n.c n.c n.c n.c n.c v dd a 3 a 2 a 1 a 0 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 100 pin qfp forward type 20 x 14 mm 2 0.65 mm pin pitch d q 2 8 v d d q d q 2 7 d q 2 6 v s s q d q 2 5 d q 2 4 v d d q d q 1 5 d q 1 4 v s s q d q 1 3 d q 1 2 v d d q v s s v d d d q 1 1 d q 1 0 v s s q d q 9 d q 8 v d d q n . c d q m 3 d q m 1 c l k c k e d s f n . c a 8 / a p 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 pin configuration description pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqmi cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one clock + t ss prior to new command. disable input buffers for power down in standby. a0 ~ a10 address row / column addresses are multiplexed on the same pins. row address : ra 0 ~ ra 10 , column address : ca 0 ~ ca 7 ba bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. dqmi data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active.(byte masking) dqi data input/output data inputs/outputs are multiplexed on the same pins. dsf define special function enables write per bit, block write and special mode register set. v dd /v ss power supply /ground power supply : +3.3v 0.3v/ground v ddq /v ssq data output power /ground provide isolated power/ground to dqs for improved noise immunity. n.c no connection *pqfp (height = 3.0mmmax) tqfp (height = 1.2mmmax)
k4g323222m cmos sgram decoupling capacitance guide line recommended decoupling capacitance added to power line at board. parameter symbol value unit decoupling capacitance between v dd and v ss c dc1 0.1 + 0.01 uf decoupling capacitance between v ddq and v ssq c dc2 0.1 + 0.01 uf 1. v dd and v ddq pins are separated each other. all v dd pins are connected in chip. all v ddq pins are connected in chip. 2. v ss and v ssq pins are separated each other all v ss pins are connected in chip. all v ssq pins are connected in chip. note : absolute maximum ratings (voltage referenced to v ss ) parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1 w short circuit current i os 50 ma permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v) parameter symbol min typ max unit note supply voltage v dd , v ddq 3.0 3.3 3.6 v 5 input high voltage v ih 2.0 3.0 v ddq +0.3 v 1 input low voltage v il -0.3 0 0.8 v 2 output high voltage v oh 2.4 - - v i oh = -2ma output low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -10 - 10 ua 3 output leakage current i lo -10 - 10 ua 4 output loading condition see figure 1 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v v out v dd. 5. the vdd condition of k4g323222m-45/50/55/60 is 3.135v~3.6v. note : capacitance (v dd /v ddq = 3.3v, t a = 23 c , f = 1mhz) pin symbol min max unit clock c clk - 4.0 pf ras , cas , we , cs , cke, dqm i ,dsf c in - 4.0 pf address c add - 4.0 pf dq i c out - 5.0 pf
k4g323222m cmos sgram dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c, v ih(min) /v il(max) =2.0v/0.8v) parameter symbol test condition cas latency speed unit note -45 -50 -55 -60 -70 -80 operating current (one bank active) i cc1 burst length =1 t rc 3 t rc (min), t cc 3 t cc (min), i o = 0ma 3 220 200 190 180 160 150 ma 2 2 - - - - - 150 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 15ns 2 ma i cc2 ps cke & clk v il (max), t cc = 2 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 30 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 15 active standby current in power-down mode i cc3 p cke v il (max), t cc = 15ns 3 ma i cc3 ps cke v il (max), t cc = 3 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 50 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 30 operating current (burst mode) i cc4 i o = 0 ma, page burst all bank activated, t ccd = t ccd (min) 3 310 290 270 260 230 200 ma 2 2 - - - - - 160 refresh current i cc5 t rc 3 t rc (min) 3 220 200 190 180 160 150 ma 3 2 - - - - - 150 self refresh current i cc6 cke 0.2v 2 ma 4 450 ua 5 operating current (one bank block write) i cc7 t cc 3 t cc (min), i o =0ma, t bwc (min) 250 230 210 200 170 150 ma 1. unless otherwise notes, input level is cmos(v ih /v il =v ddq /v ssq ) in lvttl. 2. measured with outputs open. addresses are changed only one time during tcc(min). 3. refresh period is 32ms. addresses are changed only one time during tcc(min). 4. k4g323222m-c* 5. k4g323222m-l* : low power version note :
k4g323222m cmos sgram ac operating test conditions (v dd = 3.3v 0.3v , t a = 0 to 70 c) parameter value unit input levels (v ih /v il ) 2.4 / 0.4 v input timing measurement reference level 1.4 v input rise and fall time t r / t f =1 / 1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 3.3v 1200 w 870 w output 30pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma v tt = 1.4v 50 w output 30pf z0=50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit operating ac parameter 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. refer to the following ns-unit based ac table. note : 1. the vdd condition of k4g323222m-45/50/55/60 is 3.135v~3.6v. note : (ac operating conditions unless otherwise noted) parameter symbol version unit note -45 -50 -55 -60 -70 -80 cas latency cl 3 2 3 2 3 2 3 2 3 2 3 2 clk clk cycle time t cc(min) 4.5 - 5 - 5.5 - 6 - 7 - 8 10 ns row active to row active delay t rrd(min) 2 clk 1 ras to cas delay t rcd(min) 4 - 4 - 3 - 3 - 3 - 3 2 clk 1 row precharge time t rp(min) 4 - 4 - 3 - 3 - 3 - 3 2 clk 1 row active time t ras(min) 9 - 8 - 7 - 7 - 7 - 6 5 clk 1 t ras(max) 100 us row cycle time t rc ( min ) 13 - 12 - 10 - 10 - 10 - 9 7 clk 1 last data in to row precharge t rdl(min) 2 clk 2, 5 last data in to new col.address delay t cdl(min) 1 clk 2 last data in to burst stop t bdl(min) 1 clk 2 col. address to col. address delay t ccd(min) 1 clk block write data-in to pre command t bpl(min) 2 clk block write cycle time t bwc(min) 1 clk 3 mode register set cycle time t mrs(min) 1 clk number of valid output data cas latency=3 2 ea 4 cas latency=2 1
k4g323222m cmos sgram 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf)=1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. note : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -45 -50 -55 -60 -70 -80 unit note min max min max min max min max min max min max clk cycle time cas latency=3 t cc 4.5 1000 5 1000 5.5 1000 6 1000 7 1000 8 1000 ns 1 cas latency=2 - - - - - 10 clk to valid output delay cas latency=3 t sac - 4 - 4.5 - 5 - 5.5 - 5.5 - 6 ns 1, 2 cas latency=2 - - - - - - - - - - - 6 output data hold time t oh 2 - 2 - 2 - 2.5 - 2.5 - 2.5 - ns 2 clk high pulse width cas latency=3 t ch 1.75 - 2 - 2 - 2.5 - 3 - 3 - ns 3 cas latency=2 - - - - - - - - clk low pulse width cas latency=3 t cl 1.75 - 2 - 2 - 2.5 - 3 - 3 - ns 3 cas latency=2 - - - - - - - - input setup time cas latency=3 t ss 1.2 - 1.5 - 1.5 - 1.5 - 1.75 - 2 - ns 3 cas latency=2 - - - - - - - - 2.5 input hold time t sh 0.7 - 1 - 1 - 1 - 1 - 1 - ns 3 clk to output in low-z t slz 1 - 1 - 1 - 1 - 1 - 1 - ns 2 clk to output in hi-z cas latency=3 t shz - 4 - 4.5 - 5 - 5.5 - 5.5 - 6 ns - cas latency=2 - - - - - - - - - - - 6 parameter symbol version unit -45 -50 -55 -60 -70 -80 clk cycle time t cc(min) 4.5 5 5.5 6 7 8 ns row active to row active delay t rrd(min) 9 10 11 12 14 16 ns ras to cas delay t rcd(min) 18 20 16.5 18 21 20 ns row precharge time t rp(min) 18 20 16.5 18 21 20 ns row active time t ras(min) 40.5 40 38.5 42 49 48 ns t ras(max) 100 us row cycle time t rc ( min ) 58.5 60 55 60 70 70 ns 2. minimum delay is required to complete write. 3. this parameter means minimum cas to cas delay at block write cycle only. 4. in case of row precharge interrupt, auto precharge and read burst stop. 5. for -55/60/70/80, trdl =1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv". from the next generation, trdl will be only 2clk for every clock frequency.
k4g323222m cmos sgram simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dsf dqm ba a 8 a 10 ,a 9 ,a 7 ~a 0 note register mode register set h x l l l l l x op code 1, 2 special mode register set h 1,2,7 refresh auto refresh h h l l l h l x x 3 self refresh entry l 3 exit l h l h h h x x x 3 h x x x 3 bank active & row addr. write per bit disable h x l l h h l x v row address 4, 5 write per bit enable h 4,5,9 read & column address auto precharge disable h x l h l h l x v l column address (a 0 ~a 7 ) 4 auto precharge enable h 4, 6 write & column address auto precharge disable h x l h l l l x v l column address (a 0 ~a 7 ) 4, 5 auto precharge enable h 4,5,6,9 block write & column auto precharge disable h x l h l l h x v l column address (a 0 ~a 7 ) 4, 5 auto precharge enable h 4,5,6,9 burst stop h x l h h l l x x 7 precharge bank selection h x l l h l l x v l x both banks x h clock suspend or active power down entry h l l h h h x x x h x x x exit l h x x x x x x precharge power down mode entry h l l h h h x x x h x x x exit l h l v v v v x h x x x x dqm h x v x 8 no operation command h x l h h h x x x h x x x 1. op code : operand code a 0 ~ a 10 , ba : program keys. (@mrs) a 5 , a 6 : lmr or lcr select. (@smrs) color register exists only one per dqi which both banks share. so dose mask register. color or mask is loaded into chip through dq pin. 2. mrs can be issued only at both banks precharge state. smrs can be issued only if dq s are idle. a new command can be issued at the next clock of mrs/smrs. note :
k4g323222m cmos sgram sgram vs sdram if dsf is low, sgram functionality is identical to sdram functionality . sgram can be used as an unified memory by the appropriate dsf control --> sgram=graphic memory + main memory function mrs bank active write dsf l h l h l h sgram function mrs smrs bank active with write per bit disable bank active with write per bit enable normal write block write 3. auto refresh functions as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at both precharge state. 4. ba : bank select address. if "low" at read, (block) write, row active and precharge, bank a is selected. if "high" at read, (block) write, row active and precharge, bank b is selected. if a 8 is "high" at row precharge, ba is ignored and both banks are selected. 5. it is determined at row active cycle. whether normal/block write operates in write per bit mode or not. for a bank write, at a bank row active, for b bank write, at b bank row active. terminology : write per bit =i/o mask (block) write with write per bit mode=masked(block) write 6. during burst read or write with auto precharge, new read/(block) write command cannot be issued. another bank read/(block) write command can be issued at t rp after the end of burst. 7. burst stop command is valid only at full page burst length. 8. dqm sampled at positive going edge of a clk. masks the data-in at the very clk(write dqm latency is 0) but makes hi-z state the data-out of 2 clk cycles after.(read dqm latency is 2) 9. graphic features added to sdram s original features. if dsf is tied to low, graphic functions are disabled and chip operates as a 32m sdram with 32 dq s. simplified truth table
k4g323222m cmos sgram load color load mask a 6 function a 5 function 0 disable 0 disable 1 enable 1 enable sgrams must be powered up and initialized in a predefined manner to prevent undefined operations. 1. apply power and start clock. must maintain cke= "h", dqm= "h" and the other pins are nop condition at the inputs. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. cf.) sequence of 4 & 5 may be changed. the device is now ready for normal operation. note : 1. rfu(reserved for future use) should stay "0" during mrs cycle. 2. if a 9 is high during mrs cycle, "burst read single bit write" function will be enabled. 3. the full column burst(256bit) is available only at sequential mode of burst type. 4. if lc and lm both high(1), data of mask and color register will be unknown. register programmed with mrs (note 1) (note 2) address ba a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 function rfu w.b.l tm cas latency bt burst length (note 3) test mode cas latency burst type burst length a 8 a 7 type a 6 a 5 a 4 latency a 3 type a 2 a 1 a 0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 reserved 0 1 vendor use only 0 0 1 - 1 interleave 0 0 1 2 reserved 1 0 0 1 0 2 0 1 0 4 4 1 1 0 1 1 3 0 1 1 8 8 write burst length 1 0 0 reserved 1 0 0 reserved reserved a 9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 256(full) reserved special mode register programmed with smrs address ba a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 function x lc lm x mode register field table to program modes power up sequence (note 4)
k4g323222m cmos sgram burst sequence (burst length = 4) initial address sequential interleave a 1 a 0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 burst sequence (burst length = 8) initial address sequential interleave a 2 a 1 a 0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 pixel to dq mapping(at block write) column address 3 byte 2 byte 1 byte 0 byte a 2 a 1 a 0 i/o 31 - i/o 24 i/o 23 - i/o 16 i/o 15 - i/o 8 i/o 7 - i/o 0 0 0 0 dq 24 dq 16 dq 8 dq 0 0 0 1 dq 25 dq 17 dq 9 dq 1 0 1 0 dq 26 dq 18 dq 10 dq 2 0 1 1 dq 27 dq 19 dq 11 dq 3 1 0 0 dq 28 dq 20 dq 12 dq 4 1 0 1 dq 29 dq 21 dq 13 dq 5 1 1 0 dq 30 dq 22 dq 14 dq 6 1 1 1 dq 31 dq 23 dq 15 dq 7
k4g323222m cmos sgram clock (clk) the clock input is used as the reference for all sgram opera- tions. all operations are synchronized to the positive going edge of the clock. the clock transitions must be monotonic between v il and v ih . during operation with cke high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock for proper functionality and i cc specifications. clock enable (cke) the clock enable(cke) gates the clock onto sgram. if cke goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is fro- zen as long as the cke remains low. all other inputs are ignored from the next clock cycle after cke goes low. when both banks are in the idle state and cke goes low synchronously with clock, the sgram enters the power down mode from the next clock cycle. the sgram remains in the power down mode ignoring the other inputs as long as cke remains low. the power down exit is synchronous as the internal clock is suspended. when cke goes high at least " t ss + 1 clock " before the high going edge of the clock, then the sgram becomes active from the same clock edge accepting all the input commands. bank select (ba) this sgram is organized as two independent banks of 524,288 words x 32 bits memory arrays. the ba inputs is latched at the time of assertion of ras and cas to select the bank to be used for the operation. when ba is asserted low, bank a is selected. when ba is asserted high, bank b is selected. the bank select ba is latched at bank activate, read, write mode register set and precharge operations. address input (a 0 ~ a 10 ) the 19 address bits required to decode the 524,288 word loca- tions are multiplexed into 11 address input pins(a 0 ~a 10 ). the 11 bit row address is latched along with ras and ba during bank activate command. the 8 bit column address is latched along with cas , we and ba during read or write command. nop and device deselect when ras , cas and we are high, the sgram performs no operation (nop). nop does not initiate any new operation, but is needed to complete operations which require more than sin- gle clock cycle like bank activate, burst read, auto refresh, etc. the device deselect is also a nop and is entered by asserting cs high. cs high disables the command decoder so that ras , cas , we , dsf and all the address inputs are ignored. power-up sgrams must be powered up and initialized in a pre- defined manner to prevent undefined operations. 1. power must be applied to both cke and dqm inputs to pull them high and other pins are nop condition at the inputs before or along with v dd (and v ddq ) supply. the clock signal must also be asserted at the same time. 2. after v dd reaches the desired voltage, a minimum pause of 200 microseconds is required with inputs in nop condition. 3. both banks must be precharged now. 4. perform a minimum of 2 auto refresh cycles to stabilize the internal circuitry. 5. perform a mode register set cycle to program the cas latency, burst length and burst type as the default value of mode register is undefined. at the end of one clock cycle from the mode register set cycle, the device is ready for operation. when the above sequence is used for power-up, all the outputs will be in high impedance state. the high impedance of outputs is not guaranteed in any other power-up sequence. cf.) sequence of 4 & 5 may be changed. mode register set (mrs) the mode register stores the data for controlling the various operating modes of sgram. it programs the cas latency, addressing mode, burst length, test mode and various vendor specific options to make sgram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after power up to operate the sgram. the mode register is written by asserting low on cs , ras , cas , we and dsf (the sgram should be in active mode with cke already high prior to writing the mode register). the state of address pins a 0 ~ a 10 and ba in the same cycle as cs , ras , cas , we and dsf going low is the data written in the mode register. one clock cycle is required to complete the write in the mode register. the mode register con- tents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length field uses a 0 ~ a 2 , burst type uses a 3 , addressing mode uses a 4 ~ a 6 , a 7 ~ a 8 , a 10 and ba are used for vendor specific options or test mode. and the write burst length is programmed using a 9 . a 7 ~ a 8 , a 10 and ba must be set to low for normal sgram operation. refer to table for specific codes for various burst length, addressing modes and cas latencies. device operations
k4g323222m cmos sgram bank activate the bank activate command is used to select a random row in an idle bank. by asserting low on ras and cs with desired row and bank addresses, a row access is initiated. the read or write operation can occur after a time delay of t rcd (min) from the time of bank activation. t rcd (min) is an internal timing parameter of sgram, therefore it is dependent on operating clock frequency. the minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t rcd (min) with cycle time of the clock and then rounding off the result to the next higher integer. the sgram has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. also the noise generated during sensing of each bank of sgram is high requiring some time for power supplies to recover before the other bank can be sensed reliably. t rrd (min) specifies the minimum time required between activating different banks. the number of clock cycles required between different bank activation must be calculated similar to t rcd specification. the minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t ras (min) specification before a precharge command to that active bank can be asserted. the maximum time any bank can be in the active state is determined by t ras (max). the number of cycles for both t ras (min) and t ras (max) can be calculated similar to t rcd specification. burst read the burst read command is used to access burst of data on con- secutive clock cycles from an active row in an active bank. the burst read command is issued by asserting low on cs and cas with we being high on the positive edge of the clock. the bank must be active for at least t rcd (min) before the burst read com- mand is issued. the first output appears cas latency number of clock cycles after the issue of burst read command. the burst length, burst sequence and latency from the burst read com- mand is determined by the mode register which is already pro- grammed. the burst read can be initiated on any column address of the active row. the address wraps around if the initial address does not start from a boundary such that number of out- puts from each i/o are equal to the burst length programmed in the mode register. the output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. the burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. the burst stop command is valid only at full page burst length where the output does not go into high impedance at the end of burst and the burst is wrapped around.. burst write the burst write command is similar to burst read command, and is used to write data into the sgram on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. by asserting low on cs , cas and we with valid column address, a write burst is initiated. the data inputs are provided for the initial address in the same clock cycle as the burst write command. the input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. the writing can not complete to burst length. the burst write can be terminated by issuing a burst read and dqm for blocking data inputs or burst write in the same or the other active bank. the burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrapped around. the write burst can also be terminated by using dqm for blocking data and precharging the bank "t rdl " after the last data input to be written into the active row. see dqm operation also. dqm operation the dqm is used to mask input and output operations. it works similar to oe during read operation and inhibits writing during write operation. the read latency is two cycles from dqm and zero cycle for write, which means dqm masking occurs two cycles later in the read cycle and occurs in the same cycle dur- ing write cycle. dqm operation is synchronous with the clock, therefore the masking occurs for a complete cycle. the dqm signal is important during burst interrupts of write with read or precharge in the sgram. due to asynchronous nature of the internal write, the dqm operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. dqm is also used for device selection, byte selection and bus control in a memory system. dqm0 controls dq0 to dq7, dqm1 controls dq8 to dq15, dqm2 controls dq16 to dq23, dqm3 controls dq24 to dq31. dqm masks the dq s by a byte regardless that the corresponding dq s are in a state of wpb masking or pixel masking. please refer to dqm timing diagram also. precharge the precharge operation is performed on an active bank by asserting low on cs , ras , we and a 8 /ap with valid ba of the bank to be precharged. the precharge command can be asserted anytime after t ras (min) is satisfied from the bank acti- vate command in the desired bank. "t rp " is defined as the mini- mum time required to precharge a bank. the minimum number of clock cycles required to complete row precharge is calculated by dividing "t rp " with clock cycle time and rounding up to the next higher integer. care should be taken to make sure that burst write is completed or dqm is used to inhibit writing before precharge command is asserted. the maximum time any bank can be active is specified by t ras (max). therefore, each bank has to be precharged within t ras (max) from the bank activate command. at the end of precharge, the bank enters the idle state and is ready to be activated again. device operations
k4g323222m cmos sgram entry to power down, auto refresh, self refresh and mode reg- ister set etc. is possible only when both banks are in idle state. auto precharge the precharge operation can also be performed by using auto precharge. the sgram internally generates the timing to satisfy t ras (min) and "t rp " for the programmed burst length and cas latency. the auto precharge command is issued at the same time as burst read or burst write by asserting high on a 8 /ap . if burst read or burst write command is issued with low on a 8 /ap , the bank is left active until a new command is asserted. once auto precharge command is given, no new commands are pos- sible to that particular bank until the bank achieves idle state. both banks precharge both banks can be precharged at the same time by using pre- charge all command. asserting low on cs , ras , and we with high on a 8/ap after both banks have satisfied t ras (min) require- ment, performs precharge on both banks. at the end of t rp after performing precharge all, both banks are in idle state. auto refresh the storage cells of sgram need to be refreshed every 32ms to maintain data. an auto refresh cycle accomplishes refresh of a single row of storage cells. the internal counter increments automatically on every auto refresh cycle to refresh all the rows. an auto refresh command is issued by asserting low on cs , ras and cas with high on cke and we . the auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (cke is high in the previous cycle). the time required to complete the auto refresh operation is specified by "t rc (min)". the minimum number of clock cycles required can be calculated by driving "t rc " with clock cycle time and them rounding up to the next higher integer. the auto refresh command must be followed by nop s until the auto refresh operation i s completed. both banks will be in the idle state at the end of auto refresh operation. the auto refresh is the preferred refresh mode when the sgram is being used for nor- mal data transactions. the auto refresh cycle can be performed once in 15.6us or a burst of 2048 auto refresh cycles once in 32ms. self refresh the self refresh is another refresh mode available in the sgram. the self refresh is the preferred refresh mode for data retention and low power operation of sgram. in self refresh mode, the sgram disables the internal clock and all the input buffers except cke. the refresh addressing and timing are internally generated to reduce power consumption. the self refresh mode is entered from all banks idle state by asserting low on cs , ras , cas and cke with high on we . once the self refresh mode is entered, only cke state being low matters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. the self refresh is exited by restarting the external clock and then asserting high on cke. this must be followed by nop s for a minimum time of "t rc " before the sgram reaches idle state to begin normal operation. if the system uses burst auto refresh during normal operation, it is recommended to use burst 2048 auto refresh cycles immediately after exiting self refresh. define special function(dsf) the dsf controls the graphic applications of sgram. if dsf is tied to low, sgram functions as 512k x 32 x2 bank sdram. sgram can be used as an unified memory by the appropriate dsf command. all the graphic function modes can be entered only by setting dsf high when issuing commands which other- wise would be normal sdram commands. sdram functions such as ras active, write, and wcbr change to sgram func- tions such as ras active with wpb, block write and swcbr respectively. see the section below for the graphic functions that dsf controls. special mode register set(smrs) there are two kinds of special mode registers in sgram.one is color register and the other is mask register. those usage will be explained in the "write per bit" and "block write" sec- tions. when a 5 and dsf goes high in the same cycle as cs , ras , cas and we going low, load mask register(lmr) pro- cess is executed and the mask registers are filled with the masks for associated dq s through dq pins. and when a 6 and dsf goes high in the same cycle as cs , ras , cas and we going low, load color register(lcr) process is executed and the color register is filled with color data for associated dq s through the dq pins. if both a 5 and a 6 are high at smrs, data of mask and color cycle are required to complete the write in the mask register and the color register at lmr and lcr respec- tively. a new command can be issued in the next clock of lmr or lcr. smrs, compared with mrs, can be issued at the active state under the condition that dq s are idle. as in write opera- tion, smrs accepts the data needed through dq pins. there- fore bus contention must be avoided. the more detailed materials can be obtained by referring corresponding timing dia- gram. device operations (continued)
k4g323222m cmos sgram write per bit write per bit(i.e. i/o mask mode) for sgram is a function that selectively masks bits of data being written to the devices. the mask is stored in an internal register and applied to each bit of data written when the mask is enabled. bank active command with dsf=high enables write per bit for associated bank. bank active command with dsf=low disables write per bit for the associated bank. the mask used for write per bit operations is stored in the mask register accessed by swcbr(special mode register set command). when a mask bit=1, the associated data bit is written when a write command is executed and write per bit has been enabled for the bank being written. when a mask bit=0, the associated data bit is unaltered when a write command is executed and the write per bit has been enabled for the bank being written. no additional timing conditions are required for write per bit operations. write per bit writes can be either single write, burst writes or block writes. dqm masking is the same for write per bit and non-wpb write. block write block write is a feature allowing the simultaneous writing of consecutive 8 columns of data within a ram device during a sin- gle access cycle. during block write the data to be written comes from an internal "color" register and dq i/o pins are used for independent column selection. the block of column to be written is aligned on 8 column boundaries and is defined by the column address with the 3 lsb s ignored. write command with dsf=1 enables block write for the associated bank. a write command with dsf=0 enables normal write for the associated bank. the block width is 8 column where column="n" bits for by "n" part. the color register is the same width as the data port of the chip.it is written via a swcbr where data present on the dq pin is to be coupled into the internal color register. the color register provides the data masked by the dq column select, wpb mask(if enabled), and dqm byte mask. column data mask- ing(pixel masking) is provided on an individual column basis for each byte of data. the column mask is driven on the dq pins during a block write command. the dq column mask function is segmented on a per bit basis(i.e. dq[0:7] provides the column mask for data bits[0:7], dq[8:15] provides the column mask for data bits[8:15], dq0 masks column[0] for data bits[0:7], dq9 masks column [1] for data bits [8:15], etc). block writes are always non-burst, independent of the burst length that has been programmed into the mode register. back to back block writes are allowed provided that the specified block write cycle time( t bwc ) is satisfied. if write per bit was enabled by the bank active command with dsf=1, then write per bit masking of the color register data is enabled. if write per bit was disabled by a bank active command with dsf=0, the write per bit masking of the color register data is dis- abled. dqm masking provides independent data byte masking during block write exactly the same as it does during normal write operations, except that the control is extended to the con- secutive 8 columns of the block write. 1 clk bw clock cke cs ras cas we dsf high 0 1 2 timing diagram to lllustrate t bwc device operations (continued)
k4g323222m cmos sgram summary of 4m byte sgram basic features and benefits features 512k x 32 x 2 sgram benefits interface synchronous better interaction between memory and system without wait-state of asynchronous dram. high speed vertical and horizontal drawing. high operating frequency allows performance gain for scroll, fill, and bitblt. bank 2 ea pseudo-infinite row length by on-chip interleaving operation. hidden row activation and precharge. page depth / 1 row 256 bit high speed vertical and horizontal drawing. total page depth 2048 bytes high speed vertical and horizontal drawing. burst length(read) 1, 2, 4, 8 full page programmable burst of 1, 2, ,4, 8 and full page transfer per column addresses. burst length(write) 1, 2, 4, 8 full page programmable burst of 1, 2, ,4, 8 and full page transfer per column addresses. brsw switch to burst length of 1 at write without mrs. burst type sequential & interleave compatible with intel and motorola cpu based system. cas latency 2, 3 programmable cas latency. block write 8 columns high speed fill, clear, text with color registers. maximum 32 byte data transfers(e.g. for 8bpp : 32 pixels) with plane and byte masking functions. color register 1 ea. a and b bank share. mask register 1 ea. write-per-bit capability(bit plane masking). a and b banks share. mask function dqm 0-3 byte masking(pixel masking for 8bpp system) for data-out/in write per bit each bit of the mask register directly controls a corresponding bit plane. pixel mask at block write byte masking(pixel masking for 8bpp system) for color by dqi
k4g323222m cmos sgram 1) write mask (bl=4) 2. dqm operation wr d 0 d 1 d 3 d 0 d 1 d 3 clk cmd dqmi note 1 dq(cl2) dq(cl3) masked by dqm 2) read mask (bl=4) rd q 0 q 2 q 3 q 1 q 2 q 3 masked by dqm dqm to data-in mask = 0clk dqm to data-out mask = 2clk hi-z hi-z 3) dqm with clock suspended (full page read) note 2 rd clk cmd cke dq(cl2) dq(cl3) q 0 q 4 q 7 q 8 q 2 q 3 q 6 q 7 q 1 hi-z hi-z hi-z hi-z hi-z hi-z dqm *note : 1. there are 4 dqmi(i=0~3). each dqmi masks 8 dqi s.(1 byte, 1 pixel for 8 bpp) 2. dqm makes data out hi-z after 2 clocks which should masked by cke " l". q 6 q 5 1) clock suspended during write (bl=4) 1. clock suspend wr d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 clk cmd cke internal clk dq(cl2) dq(cl3) masked by cke 2) clock suspended during read (bl=4) d 0 not written basic feature and function descriptions rd q 0 q 1 q 2 q 0 q 1 q 2 q 3 masked by cke q 3 suspended dout note : cke to clk disable/enable=1 clock
k4g323222m cmos sgram t ccd note 2 t cdl note 3 t ccd note 2 t cdl note 3 1. by " interrupt ", it is possible to stop burst read/write by external command before the end of burst. by " cas interrupt" , to stop burst read/write by cas access ; read, write and block write. 2. t ccd : cas to cas delay. (=1clk) 3. t cdl : last data in to new column address delay. (=1clk) 4. pixel :pixel mask. 5. t bwc : block write minimum cycle time. dq(cl2) dq(cl3) t ccd note 2 t cdl note 3 note 4 t bwc note 5 note 4 note 2 3. cas interrupt (i) 1) read interrupted by read (bl=4) note 1 clk cmd add 2) write interrupted by(block) write (bl=2) 3) write interrupted by read (bl=2) dq(cl2) dq(cl3) 4) block write to block write clk cmd add dq rd rd a b qa 0 qa 0 qb 0 qb 0 qb 1 qb 2 qb 3 qb 1 qb 2 qb 3 t ccd a b c d wr wr wr bw da 0 db 0 db 1 dc 0 pixel da 0 da 0 qb 0 qb 1 qb 0 qb 1 a b wr rd a b pixel pixel bw bw *note : clk cmd add dq
k4g323222m cmos sgram rd wr d 1 d 2 d 3 d 0 1. to prevent bus contention, there should be at least one gap between data in and data out. 2. to prevent bus contention, dqm should be issued which makes at least one gap between data in and data out. rd wr rd wr hi-z hi-z d 1 d 2 rd d 3 wr d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 rd wr rd wr rd wr d 1 d 2 d 3 d 0 hi-z q 0 d 1 d 2 d 3 d 0 note 1 rd wr hi-z d 1 d 2 d 3 d 0 rd wr q 0 d 1 d 2 d 3 d 0 note 2 hi-z v) cmd dqm dq dqm dq dqm dq dqm dq dqm dq (2) cl=3, bl=4 clk i) cmd ii) cmd iii) cmd iv) cmd *note : dqm dq dqm dq iv) cmd iii) cmd dqm dq dqm dq clk (1) cl=2, bl=4 i) cmd ii) cmd 4. cas interrupt (ii) : read interrupted by write & dqm d 0 d 1 d 2 d 3
k4g323222m cmos sgram note 3 auto precharge starts *note : 1. to inhibit invalid write, dqm should be issued. 2. this precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation. 3. for -55/60/70/80, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "n v" . from the next generation, trdl will be only 2clk for every clock frequency. 5. write interrupted by precharge & dqm d 0 d 1 d 2 clk cmd dqm dq masked by dqm wr pre d 3 note 2,3 note 1 *note : 1. t bpl : block write data-in to pre command delay 2. number of valid output data after row precharge : 1, 2 for cas latency =2, 3 respectively. 3. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of other activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same/another bank is illegal. 4. for -55/60/70/80, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "n v" . from the next generation, trdl will be only 2clk for every clock frequency. 6. precharge d 0 d 1 d 2 clk cmd dq wr pre d 3 1) normal write (bl=4) t rdl note 1,4 3) read (bl=4) clk cmd dq(cl2) dq(cl3) rd pre q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 1 2 note 2 7. auto precharge d 0 d 1 d 2 clk cmd dq wr d 3 1) normal write (bl=4) note 3,4 auto precharge starts 3) read (bl=4) clk cmd dq(cl2) dq(cl3) rd q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 note 3 auto precharge starts pixel clk cmd dq bw pre 2) block write t bpl note 1 clk cmd dq (cl 2, 3) 2) block write pixel bw t bpl t rp
k4g323222m cmos sgram 1. t rdl : 1 clk, last data in to row precharge. 2. t bdl : 1 clk, last data in to burst stop delay. 3. number of valid output data after row precharge or burst stop : 1, 2 for cas latency= 2, 3 respectiviely. 4. pre : both banks precharge if necessary. mrs can be issued only at all bank precharge state. 5. for -55/60/70/80, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "n v" . from the next generation, trdl will be only 2clk for every clock frequency. d 3 t rdl note 1,5 note 3 note 3 t bdl note 4 8. burst stop & precharge interrupt 1) write interrupted by precharge (bl=4) 2) write burst stop (full page only) 3) read interrupted by precharge (bl=4) 4) read burst stop (full page only) clk cmd dq(cl2) dq(cl3) clk cmd dq(cl2) dq(cl3) 9. mrs & smrs 1) mode register set 2) special mode register set clk cmd clk cmd *note : t rp 1clk 1clk 1clk 1clk 1clk clk cmd dqm dq clk cmd dq wr pre d 0 d 1 d 2 pre rd q 0 q 1 q 0 q 1 1 2 q 0 q 1 1 q 0 q 1 2 stop rd pre mrs act smrs act smrs smrs bw d 0 d 1 d 2 wr stop
k4g323222m cmos sgram 1. active power down : one or more bank active state. 2. precharge power down : both bank precharge state. 3. the auto refresh is the same as cbr refresh of conventional dram. no precharge commands are required after auto refresh command. during trc from auto refresh command, any other command can not be accepted. 4. before executing auto/self refresh command, both banks must be idle state. 5. (s)mrs, bank active, auto/self refresh, power down mode entry. 6. during self refresh mode, refresh interval and refresh operation are perfomed internally. after self refresh entry, self refresh mode is kept while cke is low. during self refresh mode, all inputs expect cke will be don t cared, and outputs will be in hi-z state. during trc from self refresh exit command, any other command can not be accepted. before/after self refresh mode, burst auto refresh cycle (2k cycles) is recommended. t ss note 1 note 5 internal clk t ss note 2 note 4 t rp t rc note 4 t rp t rc 10. clock suspend exit & power down exit 1) clock suspend (=active power down) exit 2) power down (=precharge power down) exit clk cke cmd internal clk clk cke cmd 11. auto refresh & self refresh 1) auto refresh note 3 2) self refresh note 6 clk cmd cke clk cmd cke *note : rd nop act cmd sr pre cmd ar pre ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
k4g323222m cmos sgram 12. about burst type control basic mode sequential counting at mrs a 3 = "0". see the burst sequence table. (bl=4,8) bl=1, 2, 4, 8 and full page wrap around. interleave counting at mrs a 3 = "1". see the burst sequence table. (bl=4,8) bl=4, 8. at bl=1, 2 interleave counting = sequential counting pseudo- mode pseudo- decrement sequential counting at mrs a 3 = "1".(see to interleave counting mode) starting address lsb 3 bits a 0-2 should be "000" or "111".@bl=8. -- if lsb="000" : increment counting. -- if lsb="111" : decrement counting. for example,(assume addresses except lsb 3 bits are all 0, bl=8) -- @ write, lsb="000", accessed column in order 0-1-2-3-4-5-6-7 -- @ read, lsb="111", accessed column in order 7-6-5-4-3-2-1-0 at bl=4, same applications are possible. as above example, at interleave counting mode, by confining starting address to some values, pseudo -decrement counting mode can be realized. see the burst sequence table carefully. pseudo- binary counting at mrs a 3 = "0".(see to sequential counting mode) a 0-2 = "111".(see to full page mode) using full page mode and burst stop command, binary counting mode can be realized. -- @ sequential counting, accessed column in order 3-4-5-6-7-1-2-3(bl=8) -- @ pseudo -binary counting, accessed column in order 3-4-5-6-7-8-9-10(burst stop command) note. the next column address of 256 is 0. random mode random column access t ccd = 1 clk every cycle read/write command with random column address can realize random column access. that is similar to extended data out (edo) operation of conventional dram. 13. about burst length control basic mode 1 at mrs a 2,1,0 = "000". at auto precharge, t ras should not be violated. 2 at mrs a 2,1,0 = "001". at auto precharge, t ras should not be violated. 4 at mrs a 2,1,0 = "010". 8 at mrs a 2,1,0 = "011". full page at mrs a 2,1,0 = "111". wrap around mode(infinite burst length)should be stopped by burst stop, ras interrupt or cas interrupt. special mode brsw at mrs a 9 = "1". read burst =1, 2, 4, 8, full page/write burst =1 at auto precharge of write, t ras should not be violated. block write 8 column block write. lsb a0-2 are ignored. burst length=1. t bwc should not be violated. at auto precharge, t ras should not be violated. random mode burst stop t bdl = 1, valid dq after burst stop is 1, 2 for cl=2, 3 respectively using burst stop command, it is possible only at full page burst length. interrupt mode ras interrupt (interrupted by precharge) before the end of burst, row precharge command of the same bank stops read/write burst with row precharge. t rdl = 2 with dqm, valid dq after burst stop is 1, 2 for cl= 2, 3 respectively during read/write burst with auto precharge, ras interrupt cannot be issued. cas interrupt before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. during read/write burst with auto precharge, cas interrupt can not be issued.
k4g323222m cmos sgram i/o(=dq) 31 24 23 16 15 8 7 0 external data-in 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dqmi dqm 3 =0 dqm 2 =0 dqm 1 =0 dqm 0 =1 mask register 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 0 before write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 after write 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 14. mask functions 1) normal write i/o masking : by mask at write per bit mode, the selected bit planes keep the original data. if bit plane 0, 3, 7, 9, 15, 22, 24, and 31 keep the original value. i) step - smrs(lmr) :load mask[31-0]="0111, 1110, 1011,1111, 0111, 1101, 0111, 0110" - row active with dsf "h" :write per bit mode enable - perform normal write. i) illustration i/o(=dq) 31 24 23 16 15 8 7 0 dqmi dqm 3 =0 dqm 2 =0 dqm 1 =0 dqm 0 =1 color register color3=blue color2=green color1=yellow color0=red before block write & dq (pixel data) 000 white dq 24 =h white dq 16 =h white dq 8 =h white dq 0 =l 001 white dq 25 =h white dq 17 =h white dq 9 =l white dq 1 =h 010 white dq 26 =h white dq 18 =l white dq 10 =h white dq 2 =h 011 white dq 27 =l white dq 19 =h white dq 11 =h white dq 3 =h 100 white dq 28 =h white dq 20 =h white dq 12 =h white dq 4 =l 101 white dq 29 =h white dq 21 =h white dq 13 =l white dq 5 =h 110 white dq 30 =h white dq 22 =l white dq 14 =h white dq 6 =h 111 white dq 31 =l white dq 23 =h white dq 15 =h white dq 7 =h after block write 000 blue green yellow white 001 blue green white white 010 blue white yellow white 011 white green yellow white 100 blue green yellow white 101 blue green white white 110 blue white yellow white 111 white green yellow white 2) block write pixel masking : by pixel data issued through dq pin, the selected pixels keep the original data. see pixel to dq mapping table. if pixel 0, 4, 9, 13, 18, 22, 27 and 31 keep the original white color. assume 8bpp, white = "0000,0000", red="1010,0011", green = "1110,0001", yellow = "0000,1111", blue = "1100,0011" i) step - smrs(lcr) :load color(for 8bpp, through x32 dq color0-3 are loaded into color registers) load(color3, color2, color1, color0) = (blue, green, yellow, red) = "1100,0011, 1110, 0001, 0000, 1111, 1010, 0011" - row active with dsf "l" : i/o mask by write per bit mode disable - block write with dq[31-0] = "0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110" i) illustration 1. dqm byte masking. 2. at normal write, one column is selected among columns decorded by a 2-0 (000-111). at block write, instead of ignored address a 2-0 , dq 0-31 control each pixel. note 1 note 2 *note :
k4g323222m cmos sgram i/o(=dq) 31 24 23 16 15 8 7 0 color register blue 1 1 0 0 0 0 1 1 green 1 1 1 0 0 0 0 1 yellow 0 0 0 0 1 1 1 1 red 1 0 1 0 0 0 1 1 dqmi dqm 3 =0 dqm 2 =0 dqm 1 =0 dqm 0 =1 mask register 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 1 0 before write yellow 0 0 0 0 1 1 1 1 yellow 0 0 0 0 1 1 1 1 green 1 1 1 0 0 0 0 1 white 0 0 0 0 0 0 0 0 after write blue 1 1 0 0 0 0 1 1 blue 1 1 0 0 0 0 1 1 red 1 0 1 0 0 0 1 1 white 0 0 0 0 0 0 0 0 (continued) pixel and i/o masking : by mask at write per bit mode, the selected bit planes keep the original data. by pixel data issued through dq pin, the selected pixels keep the original data. see pixel to dq mapping table. assume 8bpp, white = "0000,0000", red="1010,0011", green ="1110,0001", yellow ="0000,1111", blue ="1100,0011" i) step - smrs(lcr) : load color(for 8bpp, through x 32 dq color0-3 are loaded into color registers) load(color3, color2, color1, color0) = (blue, green, yellow, red) = "1100,0011,1110,0001,0000,1111,1010,0011" - smrs(lmr ): load mask. mask[31-0] ="1111,1111,1101,1101, 0100,0010,0111,0110" --> byte 3 : no i/o masking ; byte 2 : i/o masking ; byte 1 : i/o and pixel masking ; byte 0 : dqm byte maskin g - row active with dsf "h" : i/o mask by write per bit mode enable - block write with dq[31-0] = "0111,0111,1111,1111,0101,0101,1110,1110" (pixel mask) i) illustration note 2 note 1 i/o(=dq) 31 24 23 16 15 8 7 0 dqmi dqm 3 =0 dqm 2 =0 dqm 1 =0 dqm 0 =1 color register color3=blue color2=green color1=yellow color0=red before block write & dq (pixel data) 000 yellow dq 24 =h yellow dq 16 =h green dq 8 =h white dq 0 =l 001 yellow dq 25 =h yellow dq 17 =h green dq 9 =l white dq 1 =h 010 yellow dq 26 =h yellow dq 18 =h green dq 10 =h white dq 2 =h 011 yellow dq 27 =l yellow dq 19 =h green dq 11 =l white dq 3 =h 100 yellow dq 28 =h yellow dq 20 =h green dq 12 =h white dq 4 =l 101 yellow dq 29 =h yellow dq 21 =h green dq 13 =l white dq 5 =h 110 yellow dq 30 =h yellow dq 22 =h green dq 14 =h white dq 6 =h 111 yellow dq 31 =l yellow dq 23 =h green dq 15 =l white dq 7 =h after block write 000 blue blue red white 001 blue blue green white 010 blue blue red white 011 yellow blue green white 100 blue blue red white 101 blue blue green white 110 blue blue red white 111 yellow blue green white 1. dqm byte masking. 2. at normal write, one column is selected among columns decorded by a 2-0 (000-111). at block write, instead of ignored address a 2-0 , dq 0-31 control each pixel. pixel mask i/o mask pixel & i/o mask byte mask *note : note 1
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 power on sequence & auto refresh clock cke cs ras cas addr ba a 8 /ap dq we dqm ra trp trc high level is necessary high-z high level is necessary : don t care precharge auto refresh auto refresh mode register set (all banks) dsf ra bs key key key row active (write per bit enable or disable) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *note 5 row active read write read row active precharge single bit read-write-read cycle(same page) @cas latency=3, burst length=1 t rcd *note 1 t ss t sh t rp t ccd t ss t sh t rac t sac t slz t sh t sh t ss t ss t sh t ss t sh clock cke cs ras cas addr ba a 8 /ap dq we dqm high t sh t sh t ss t ss *note 2,3 *note 2,3 *note 4 *note 4 *note 3 *note 3 *note 3 rb cc cb ca ra bs bs bs bs bs bs ra rb qc db qa *note 2,3 *note 2 *note 2 t ss t sh dsf *note 5 *note 6 *note 3 t ch t cc t cl t ras t rc t ss t oh t shz (write per bit enable or disable) or block write (write per bit enable or disable) : don t care
k4g323222m cmos sgram 1. all input can be don't care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by ba. ba active & read/write 0 bank a 1 bank b a 8 /ap ba operation 0 0 disable auto precharge, leave bank a active at end of burst. 1 disable auto precharge, leave bank b active at end of burst. 1 0 enable auto precharge, precharge bank a at end of burst. 1 enable auto precharge, precharge bank b at end of burst. a 8 /ap ba precharge 0 0 bank a 0 1 bank b 1 x both bank ba dsf operation 0 l bank a row active, disable write per bit function for bank a h bank a row active, enable write per bit function for bank a 1 l bank b row active, disable write per bit function for bank b h bank b row active, enable write per bit function for bank b dsf operation minimum cycle time l normal write t ccd h block write t bwc 3. enable and disable auto precharge function are controlled by a 8 /ap in read/write command. 4. a 8 /ap and ba control bank precharge when precharge command is asserted. 5. enable and disable write-per bit function are controlled by dsf in row active command. 6. block write/normal write is controlled by dsf. *note :
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read & write cycle at same bank @burst length=4 high row active (a-bank) precharge (a-bank) row active (a-bank) write (a-bank) precharge (a-bank) *note : 1. minimum row cycle times is required to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. [cas latency - 1] valid output data available after row enters precharge. last valid output will be hi-z after t shz from the clcok. 3. access time from row address. t cc *( t rcd + cas latency - 1) + t sac 4. ouput will be hi-z after the end of burst. (1, 2, 4, & 8). at full page bit burst, burst is wrap-around. 5. for -55/60/70/80, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" . from the next generation, trdl will be only 2clk for every clock frequency. read (a-bank) *note 1 t rc t rcd *note 2 t rdl t rdl t shz *note 4 t shz *note 4 t oh t rac *note 3 t sac t sac t rac *note 3 t oh ba a 8 /ap addr cas ras cs cke clock ra rb qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 db0 db1 db2 db3 ra ca0 rb cb0 we dqm dsf : don t care (cl=2) (cl=3) dq dq *note 5 *note 5
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *note 3 page read & write cycle at same bank @burst length=4 high row active (a-bank) read (a-bank) write (a-bank) precharge (a-bank) 1. to write data before burst read ends, dqm should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 4. for -55/60/70/80, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" . from the next generation, trdl will be only 2clk for every clock frequency. read (a-bank) t rcd *note 2 *note 1 t cdl qa0 qa1 qb0 qb1 qa0 qa1 qb0 dc0 dc1 dd0 dd1 dc0 dc1 dd0 dd1 write (a-bank) ba a 8 /ap addr cas ras cs cke clock we dqm ra ca0 cb0 cc0 cd0 ra dsf t rdl *note 2 : don t care *note : (cl=2) (cl=3) dq dq *note 4
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 block write cycle(with auto precharge) high row active with write-per-bit enable (a-bank) masked block write with auto precharge (a-bank) block write (b-bank) row active (b-bank) 1. column mask(dqi=l : mask, dqi=h :non mask) 2. at b lock write, ca 0~2 are ignored. masked block write (a-bank) t bwc block write with auto precharge (b-bank) ba a 8 /ap addr cas ras cs cke clock we dqm raa caa cab cba cbb raa dsf rba rba dq pixel mask pixel mask pixel mask pixel mask *note 1 *note 2 *note : : don t care
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 smrs and block/normal write @ burst length=4 high load color register masked block write (a-bank) load color register row active with wpb* enable (b-bank) load mask register *note 1 masked write with auto precharge (b-bank) a 3,4,7,8 a 5 a 0-2 cas ras cs cke clock we dqm raa rba cba dsf dq a 8 /ap ba a 6 raa rba cba caa raa rba cba caa raa rba cba caa raa rba color i/o mask pixel mask i/o mask color dba0 dba1 dba2 dba3 row active with wpb* enable (a-bank) *note : 1. at the next clock of special mode set command, new command is possible. load mask register wpb* : write-per-bit : don t care
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 page read cycle at different bank @burst length=4 high row active (a-bank) row active (b-bank) read (a-bank) read (b-bank) 1. cs can be don t care when ras , cas and we are high at the clock high going edge. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same. read (a-bank) *note 2 *note 1 read (b-bank) read (a-bank) precharge (a-bank) ba a 8 /ap addr cas ras cs cke clock we dqm raa rbb raa rbb caa cbb cbd cac cae qaa0 qaa1 qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1 qaa0 qaa1 qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1 dsf low *note : : don t care (cl=2) (cl=3) dq dq
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 page write cycle at different bank @burst length=4 high row active with write-per-bit enable (a-bank) row active (b-bank) masked write with auto precharge (a-bank) masked write (a-bank) write with auto precharge (b-bank) t cdl write (b-bank) ba dq addr cas ras cs cke clock we dqm a 8 /ap raa caa cbb cac raa daa0 daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 dac2 dac3 rbb rbb key cbd dsf mask dbd0 dbd1 dbd2 dbd3 load mask register : don t care
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read & write cycle at different bank @burst length=4 high row active (a-bank) write (b-bank) row active (a-bank) read (a-bank) *note 1 t cdl row active (b-bank) precharge (a-bank) read (a-bank) ba a 8 /ap addr cas ras cs cke clock we dqm qaa0 qaa1 qaa2 qaa3 qaa0 qaa1 qaa2 qaa3 dbb0 dbb1 dbb2 dbb3 dbb0 dbb1 dbb2 dbb3 qac0 qac1 qac2 qac0 qac1 raa caa rbb cbb rac cac rac raa rbb dsf : don t care *note : 1. t cdl should be met to complete write. (cl=2) (cl=3) dq dq
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read & write cycle with auto precharge i @burst length=4 high row active (a-bank) 1. t rcd should be controlled to meet minimum t ras before internal precharge start. (in the case of burst length=1 & 2, brsw mode and block write) row active (b-bank) read with auto precharge (a-bank) auto precharge start point (b-bank) auto precharge start point (a-bank) write with auto precharge (b-bank) addr cas ras cs cke clock we dqmi raa rbb caa rbb cbb dsf *note : : don t care (cl=2) (cl=3) dq dq raa qaa0 qaa1 qaa2 qaa3 qaa0 qaa1 qaa2 qaa3 dbb0 dbb1 dbb2 dbb3 dbb0 dbb1 dbb2 dbb3 ba a 8 /ap
k4g323222m cmos sgram read without auto precharge(b-bank) auto precharge start point (a-bank) read & write cycle with auto precharge ii @burst length=4 high row active (a-bank) : don t care *note: 1. when read(write) command with auto precharge is issued at a-bank after a and b bank activation. - if read(write) command without auto precharge is issued at b-bank before a bank auto precharge starts, a bank auto precharge will start at b bank read command input point . - any command can not be issued at a bank during trp after a bank auto precharge starts. row active (b-bank) read with auto pre charge (a-bank) write with auto precharge (a-bank) row active (a-bank) addr cas ras cs cke clock we dqm qa0 qa1 qb0 qb1 qa0 qa1 qb0 qb1 ra rb ca ra rb ra cb qb2 qb3 precharge (b-bank) ca ra da0 da1 da0 da1 qb2 qb3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 (cl=2) (cl=3) dq dq dsf *note 1 ba a 8 /ap
k4g323222m cmos sgram read & write cycle with auto precharge iii @burst length=4 high row active (a-bank) : don t care *note : 1. any command to a-bank is not allowed in this period. trp is determined from at auto precharge start point read with auto precharge (a-bank) auto precharge start point (a-bank) row active (b-bank) read with auto precharge (b-bank) addr cas ras cs cke clock we qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qb0 qb1 qb2 qb3 ra ca ra cb rb rb auto precharge start point (b-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 dqm dsf (cl=2) (cl=3) dq dq *note 1 ba a 8 /ap
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read interrupted by precharge command & read burst stop cycle (@full page only) high row active (a-bank) 1. at full page mode, burst is wrap-around at the end of burst. so auto precharge is impossible. 2. about the valid dq s after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing diagram. see the label 1, 2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of "full page write burst stop cycle". *note 1 precharge (a-bank) read (a-bank) read (a-bank) 1 2 1 2 ba a 8 /ap addr cas ras cs cke clock we dqm qaa0 qaa1 qaa2 qaa3 qaa4 qaa0 qaa1 qaa2 qaa3 qaa4 qab0 qab1 qab2 qab3 qab4 qab5 qab0 qab1 qab2 qab3 qab4 qab5 raa caa cab raa *note 1 dsf *note 2 : don t care burst stop *note : (cl=2) (cl=3) dq dq
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 write interrupted by precharge command & write burst stop cycle (@ full page only) row active (a-bank) write (a-bank) precharge (a-bank) write (a-bank) *note 3 tbdl 1. at full page mode, burst is wrap-around at the end of burst. so auto precharge is impossible. 2. data-in at the cycle of burst stop command cannot be written into the corresponding memory cell. it is defined by ac parameter of t bdl (=1clk). 3. data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. it is defined by ac parameter of t rdl (=2clk). dqm at write interrupted by precharge command is needed to ensure t rdl of 2clk. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 4. burst stop is valid only at full page burst length. 5. for -55/60/70/80, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" . from the next generation, trdl will be only 2clk for every clock frequency. high t rdl ba dq addr cas ras cs cke clock we dqm a 8 /ap daa0 daa1 daa2 daa3 daa4 dab0 dab1 dab2 dab3 dab4 dab5 raa caa cab raa dsf *note 1 *note 1 *note 2 burst stop *note : : don t care *note 5
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *note 1 burst read single bit write cycle @burst length=2, brsw high row active (a-bank) row active (a-bank) write with auto precharge (b-bank) 1. brsw mode is enabled by setting a 9 "high" at mrs (mode register set). at the brsw mode, the burst length at write is fixed to "1" regardless of programed burst length. 2. when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the burst-end cycle, so in the case of brsw write command, the next cycle starts the precharge. 3. wpb function is also possible at brsw mode. write (a-bank) row active (b-bank) read (a-bank) read with auto precharge (a-bank) precharge (a-bank) *note 2 ba a 8 /ap addr cas ras cs cke clock we dqmi daa0 daa0 qab0 qab1 qab0 qab1 dbc0 dbc0 qad0 qad1 qad0 qad1 raa caa rbb cab rac cbc cad rac raa rbb dsf *note : : don t care (cl=2) (cl=3) dq dq
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock suspension & dqm operation cycle @cas latency=2, burst length=4 clock suspension clock suspension *note 1 t sh z t sh z write dqm ba dq addr cas ras cs cke clock we dqm a 8 /ap ra ca cb cc dc2 dc0 qb1 qb0 qa3 qa2 qa1 qa0 ra dsf : don t care *note : 1. dqm needed to prevent bus contention. row active read read read dqm write
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 active/precharge power down mode @cas lantency=2, burst length=4 precharge power-down entry 1. all banks should be in idle state prior to entering precharge power down mode. 2. cke should be set high at least "1clk + t ss " prior to row active command. 3. cannot violate minimum refresh specification. (32ms) *note 1 t ss *note 2 ba dq addr cas ras cs cke clock we dqm a 8 /ap t ss t ss ra ca ra qa0 qa1 qa2 active power-down entry active power-down exit *note 3 dsf t ss precharge power-down exit row active read precharge : don t care *note : ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
k4g323222m cmos sgram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 self refresh entry & exit cycle to enter self refresh mode 1. cs , ras & cas with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don t care except for cke. 3. the device remains in self refresh mode as long as cke stays "low". cf.) once the device enters self refresh mode, minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum t rc is required after cke going high to complete self refresh exit. 7. 2k cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. *note 1 *note 7 hi-z hi-z t ss *note 2 *note 3 *note 4 t rc min. *note 6 *note 5 ba dq addr cas ras cs cke clock we dqm a 8 /ap dsf *note 7 t ss self refresh entry self refresh exit auto refresh : don t care *note : ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
k4g323222m cmos sgram 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 mode register set cycle high 1. cs , ras , cas , & we activation and dsf of low at the same clock cycle with address key will set internal mode register. 2. minimum 1 clock cycles should be met before new ras activation. 3. please refer to mode register set table. new command hi-z hi-z t rc high auto refresh cycle dq addr cas ras cs cke clock we dqm key ra *note 3 *note 1 *note 2 dsf mrs auto refresh new command : don t care * both banks precharge should be completed before mode register set cycle and auto refresh cycle. mode register set cycle *note : ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
k4g323222m cmos sgram function truth table(table 1) current state cs ras cas we dsf ba addr action note idle h x x x x x x nop l h h h x x x nop l h h l x x x illegal 2 l h l x x ba ca illegal 2 l l h h l ba ra row active ; latch row address ; non-io mask l l h h h ba ra row active ; latch row address ; io mask l l h l l ba pa nop 4 l l h l h x x illegal l l l h l x x auto refresh or self refresh 5 l l l h h x x illegal l l l l l op code mode register access 5 l l l l h op code special mode register access 6 row active h x x x x x x nop l h h h x x x nop l h h l x x x illegal 2 l h l h l ba ca,ap begin read ; latch ca ; determine ap l h l h h x x illegal l h l l l ba ca,ap begin write ;latch ca ; determine ap l h l l h ba ca,ap block write ;latch ca ; determine ap l l h h x ba ra illegal 2 l l h l l ba pa precharge l l h l h x x illegal l l l h x x x illegal l l l l l x x illegal l l l l h op code special mode register access 6 read h x x x x x x nop(continue burst to end --> row active) l h h h x x x nop(continue burst to end --> row active) l h h l l x x term burst --> row active l h h l h x x illegal l h l h l ba ca,ap term burst ; begin read ; latch ca ; determine ap 3 l h l h h x x illegal l h l l l ba ca,ap term burst ; begin write ; latch ca ; determine ap 3 l h l l h ba ca.ap term burst ; block write ; latch ca ; determine ap 3 l l h h x ba ra illegal 2 l l h l l ba pa term burst ; precharge timing for reads 3 l l h l h x x illegal l l l x x x x illegal write h x x x x x x nop(continue burst to end --> row active) l h h h x x x nop(continue burst to end --> row active) l h h l l x x term burst --> row active l h h l h x x illegal l h l h l ba ca,ap term burst ; begin read ; latch ca ; determine ap 3 l h l h h x x illegal l h l l l ba ca,ap term burst ; begin write ; latch ca ; determine ap 3 l h l l h ba ca,ap term burst ; block write ; latch ca ; determine ap 3
k4g323222m cmos sgram function truth table(table 1, continued) current state cs ras cas we dsf ba addr action note write l l h h x ba ra illegal 2 l l h l l ba pa term burst : precharge timing for writes 3 l l h l h x x illegal l l l x x x x illegal read with auto precharge h x x x x x x nop(continue burst to end --> precharge) l h h h x x x nop(continue burst to end --> precharge) l h h l x x x illegal l h l h x ba ca,ap illegal 2 l h l l x ba ca,ap illegal 2 l l h x x ba ra,pa illegal l l l x x x x illegal 2 write with auto precharge h x x x x x x nop(continue burst to end --> precharge) l h h h x x x nop(continue burst to end --> precharge) l h h l x x x illegal l h l h x ba ca,ap illegal 2 l h l l x ba ca,ap illegal 2 l l h x x ba ra,pa illegal l l l x x x x illegal 2 precharging h x x x x x x nop --> idle after t rp l h h h x x x nop --> idle after t rp l h h l x x x illegal l h l x x ba ca,ap illegal 2 l l h h x ba ra illegal 2 l l h l x ba pa nop --> idle after t rp 2 l l l x x x x illegal 4 block write recovering h x x x x x x nop --> row active after t bwc l h h h x x x nop --> row active after t bwc l h h l x x x illegal l h l x x ba ca,ap illegal 2 l l h h x ba ra illegal 2 l l h l x ba pa term block write : precharge timing for block write 2 l l l x x x x illegal 2 row activating h x x x x x x nop --> row active after t rcd l h h h x x x nop --> row active after t rcd l h h l x x x illegal l h l x x ba ca,ap illegal 2 l l h h x ba ra illegal 2 l l h l x ba pa illegal 2 l l l x x x x illegal 2 refreshing h x x x x x x nop --> idle after t rc l h h x x x x nop --> idle after t rc l h l x x x x illegal l l h x x x x illegal l l l x x x x illegal
k4g323222m cmos sgram 1. all entries assume that cke was active(high) during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state ; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba(and pa). 5. illegal if any banks is not idle. 6. legal only if all banks are in idle or row active state. ra = row address(a 0 ~a 10 ) nop = no operation command ba = bank address ca = column address(a 0 ~a 7 ) pa = precharge all(a 8 ) ap = auto precharge(a 8 ) function truth table for cke(table 2) current state cke n-1 cke n cs ras cas we dsf addr action note self refresh h x x x x x x x invalid l h h x x x x x exit self refresh --> abi after t rc 7 l h l h h h x x exit self refresh --> abi after t rc 7 l h l h h l x x illegal l h l h l x x x illegal l h l l x x x x illegal l l x x x x x x nop(maintain self refresh) both bank precharge power down h x x x x x x x invalid l h h x x x x x exit power down --> abi 8 l h l h h h x x exit power down --> abi 8 l h l h h l x x illegal l h l h l x x x illegal l h l l x x x x illegal l l x x x x x x nop(maintain power down mode) all banks idle h h x x x x x x refer to table 1 h l h x x x x x enter power down 9 h l l h h h x x enter power down 9 h l l h h l x x illegal h l l h l x x x illegal h l l l h h l ra row (& bank) active h l l l l h l x enter self refresh 9 h l l l l l l op code mode register access h l l l l l h op code special mode register access l l x x x x x x nop any state other than listed above h h x x x x x x refer to operations in table 1 h l x x x x x x begin clock suspend next cycle 10 l h x x x x x x exit clock suspend next cycle 10 l l x x x x x x maintain clock suspend 7. after cke s low to high transition to exist self refresh mode. and a time of t rc (min) has to be elapse after cke s low to high transition to issue a new command. 8. cke low to high transition is asynchronous as if restarts internal clock. a minimum setup time " t ss + one clock" must be satisfied before any command other than exit. 9. power-down and self refresh can be entered only from the all banks idle state. 10. must be a legal command. function truth table (table 1, continued) abbreviations *note : abbreviations : abi = all banks idle *note :
k4g323222m cmos sgram 0.825 0 . 5 7 5 0.65 0.13 max package dimensions (tqfp) dimensions in millimeters 0.10 max 0 ~ 7 17.20 0.20 14.00 0.10 23.20 0.20 1.00 0.10 1.20 max * 0.05 min 0.80 0.20 #1 0.09~0.20 #100 0.30 0.08 20.00 0.10 * all package dimensions of pqfp & tqfp are same except height. - pqfp (height = 3.0mmmax) - tqfp (height = 1.2mmmax)

▲Up To Search▲

Price & Availability of K4G323222M-PL70

	To Download K4G323222M-PL70 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .